Integrated circuit stress control system

ABSTRACT

An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.

TECHNICAL FIELD

The present invention relates generally to semiconductor transistors,and more particularly to transistor structures for integrated circuits.

BACKGROUND ART

At the present time, electronic products are used in almost every aspectof life, and the heart of these electronic products is the integratedcircuit. Integrated circuits are used in everything from airplanes andtelevisions to wristwatches.

Integrated circuits are made in and on silicon wafers by extremelycomplex systems that require the coordination of hundreds or eventhousands of precisely controlled processes to produce a finishedsemiconductor wafer. Each finished semiconductor wafer has hundreds totens of thousands of integrated circuits, each wafer worth hundreds orthousands of dollars.

Integrated circuits are made up of hundreds to millions of individualcomponents. One common component is the semiconductor transistor. Themost common and important semiconductor technology presently used issilicon-based, and the most preferred silicon-based semiconductor deviceis a complementary metal oxide semiconductor (“CMOS”) transistor.

CMOS transistors are generally divided into two classes, metal oxidesemiconductor with n-type channel (“NMOS”) and metal oxide semiconductorwith p-type channel (“PMOS”). NMOS is a device where electrons areresponsible for conduction. On the other hand, PMOS is a device whereholes are responsible for conduction.

The principal elements of a CMOS transistor generally consist of asilicon substrate having transistor areas. The transistor areas containpolysilicon gates on silicon oxide gates, or gate oxides, over thesilicon substrate. The silicon substrate on both sides of thepolysilicon gate is lightly doped to become conductive. These lightlydoped regions of the silicon substrate are referred to as “shallowsource/drain”, which are separated by a channel region beneath thepolysilicon gate. A curved silicon oxide or silicon nitride spacer,referred to as a “sidewall spacer”, on the sides of the polysilicon gateallows deposition of additional doping to form more heavily and deeplydoped regions of the shallow source/drain (“S/D”), which are called“deep S/D”.

To complete the transistor, a silicon oxide dielectric layer isdeposited to cover the polysilicon gate, the curved spacer, and thesilicon substrate. To provide electrical connections for the transistor,openings are etched in the silicon oxide dielectric layer to thepolysilicon gate and the S/D. The openings are filled with metal to formelectrical contacts. To complete the integrated circuits, the contactsare connected to the outside of the dielectric material throughadditional levels of wiring in additional levels of dielectric material.

Another key issue for fabrication of CMOS is mechanisms to improveperformance. One way to improve performance is to control strain in thechannel. Increasing strain to the channel improves performance in PMOS.PMOS strain can be increased, for example, by incorporating a shallowtrench isolation (“STI”). However, decreasing strain to the channelimproves performance in NMOS. Thus, it is counterproductive toincorporate an STI into an NMOS device.

An integrated circuit contains many NMOS and PMOS devices. If STIs areincorporated to improve PMOS device performance, NMOS device performancewill be degraded. What is needed is a way to enable STIs to beincorporated to improve PMOS device performance without degrading NMOSdevice performance.

Solutions to these problems have been long sought but prior developmentshave not taught or suggested any solutions and, thus, solutions to theseproblems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit stress controlsystem. A substrate is provided. A gate is formed on the substrate and achannel is formed in the substrate. A source/drain is formed around thegate. A shallow trench isolation is formed in the substrate, the shallowtrench isolation producing strain on the channel. A stress suppressingfeature is formed in the substrate.

Certain embodiments of the invention have other advantages in additionto or in place of those mentioned above. The advantages will becomeapparent to those skilled in the art from a reading of the followingdetailed description when taken with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of an integrated circuit according to anembodiment of the present invention, the cross section being taken alongline 1-1 in FIG. 2;

FIG. 2 is a top view of the integrated circuit of FIG. 1;

FIG. 3 is a top view of an integrated circuit according to an alternateembodiment of the present invention; and

FIG. 4 is a flow chart of a method for an integrated circuit stresscontrol system in accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given toprovide a thorough understanding of the invention. However, it will beapparent that the invention may be practiced without these specificdetails. In order to avoid obscuring the present invention, somewell-known circuits, system configurations, and process steps are notdisclosed in detail.

Likewise, the drawings showing embodiments of the device aresemi-diagrammatic and not to scale and, particularly, some of thedimensions are for the clarity of presentation and are shown greatlyexaggerated in the FIGs. In addition where multiple embodiments aredisclosed and described having some features in common, for clarity andease of illustration, description, and comprehension thereof, likefeatures one to another will ordinarily be described with like referencenumerals.

The term “horizontal” as used herein is defined as a plane parallel tothe conventional plane or surface of the substrate, regardless of itsorientation. The term “vertical” refers to a direction perpendicular tothe horizontal as just defined. Terms, such as “on”, “above”, “below”,“bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”,and “under”, are defined with respect to the horizontal plane.

The term “processing” as used herein includes deposition of material orphotoresist, patterning, exposure, development, etching, cleaning,and/or removal of the material or photoresist as required in forming adescribed structure.

Integrated circuits are made up of hundreds to millions of individualcomponents. One common component is the semiconductor transistor. Themost common and important semiconductor technology presently used issilicon (“Si”) based, and the most preferred Si based semiconductordevice is a complementary metal oxide semiconductor (“CMOS”) transistor.

CMOS transistors are generally divided into two classes, metal oxidesemiconductor with n-type channel (“NMOS”) and metal oxide semiconductorwith p-type channel (“PMOS”). NMOS is a device where electrons areresponsible for conduction. On the other hand, PMOS is a device whereholes are responsible for conduction.

The principal elements of a CMOS transistor generally consist of a Sisubstrate having transistor areas. The transistor areas containpolysilicon gates on silicon oxide gates, or gate oxides, over the Sisubstrate. The Si substrate on both sides of the polysilicon gate islightly doped to become conductive. These lightly doped regions of theSi substrate are referred to as “shallow source/drain”, which areseparated by a channel region beneath the polysilicon gate. A curvedsilicon oxide or silicon nitride spacer, referred to as a “sidewallspacer”, on the sides of the polysilicon gate allows deposition ofadditional doping to form more heavily and deeply doped regions of theshallow source/drain (“S/D”), which are called “deep S/D”.

To complete the transistor, a silicon oxide dielectric layer isdeposited to cover the polysilicon gate, the curved spacer, and the Sisubstrate. To provide electrical connections for the transistor,openings are etched in the silicon oxide dielectric layer to thepolysilicon gate and the S/D. The openings are filled with metal to formelectrical contacts. To complete the integrated circuits, the contactsare connected to the outside of the dielectric material throughadditional levels of wiring in additional levels of dielectric material.

Another key issue for fabrication of CMOS is mechanisms to improveperformance. One way to improve performance is to control strain in thechannel. Increasing strain to the channel improves performance in PMOS.PMOS strain can be increased, for example, by incorporating a shallowtrench isolation (“STI”). However, decreasing strain to the channelimproves performance in NMOS. Thus, conflicts with strain optimizationcan occur within integrated circuits incorporating both PMOS and NMOS.

Referring now to FIG. 1, therein is shown a portion of a cross sectionof an integrated circuit (“IC”) 100 taken along line 1-1 in FIG. 2,according to an embodiment of the present invention. Standard processes,such as photolithography, form an NMOS transistor 102 and a PMOStransistor 104 in a substrate 106.

In this embodiment, the NMOS transistor 102 has an NMOS gate 108. Belowthe NMOS gate 108 is an NMOS gate oxide 110, and below the NMOS gateoxide 110 is an NMOS channel 112. Surrounding the NMOS gate 108 is anNMOS liner 114, and surrounding the NMOS liner 114 is an NMOS spacer116. An NMOS source/drain 118 extends from the NMOS channel 112 in thesubstrate 106.

The PMOS transistor 104 has a PMOS gate 120. Below the PMOS gate 120 isa PMOS gate oxide 122, and below the PMOS gate oxide 122 is a PMOSchannel 124. Surrounding the PMOS gate 120 is a PMOS liner 126, andsurrounding the PMOS liner 126 is a PMOS spacer 128. A PMOS source/drain130 extends from the PMOS channel 124 in the substrate 106.

A shallow trench isolation (“STI”) 132 in the substrate 106 surroundsthe NMOS transistor 102 and the PMOS transistor 104. In this embodiment,the STI 132 is made of silicon dioxide (“SiO₂”) and the substrates 106is made of Si. Thus, the difference in thermal expansion between theSiO₂ and the Si produces strain in the PMOS channel 124 and in the NMOSchannel 112. Strain in the PMOS channel 124 improves performance byincreasing hole mobility. However, strain in the NMOS channel 112degrades performance by reducing electron mobility.

It has been unexpectedly discovered that incorporating a stresssuppressing feature 134, which is generally rectangular, parallel to thelength of the NMOS gate 108 and in the STI 132 reduces strain to theNMOS channel 112. Thus, the stress suppressing feature 134 isperpendicular to the direction of the strain. The stress suppressingfeature 134 acts similarly as a bulwark in the sea that is used tosuppress the tide from the sea. Likewise, the stress suppressing feature134, in the vicinity thereof, suppresses the strain generated by the STI132.

In one embodiment, the stress suppressing feature 134 is formed duringphotolithographic processes used to form the STI 132. A mask is used toshield the regions where the stress suppressing feature 134 will beformed. The STI 132 is then formed around the stress suppressing feature134. Thus in this embodiment, the stress suppressing feature 134 is aregion of the substrate 106 that has not been formed into the STI 132,but instead remains unaltered by the STI-forming process.

The distance between the stress suppressing feature 134 and the NMOStransistor 102 affects the strain on the NMOS transistor 102. Strainincreases as the distance increases. Thus, strain is controlled,adjusted to a predetermined level, and optimized by adjusting theposition of the stress suppressing feature 134 and adjusting thedistance between the stress suppressing feature 134 and the NMOStransistor 102.

Referring now to FIG. 2, therein is shown a top view of the IC 100. TheSTI 132 surrounds the NMOS transistor 102 and the PMOS transistor 104.The PMOS source/drain 130 are on either side of the PMOS gate 120. TheNMOS source/drain 118 are on either side of the NMOS gate 108. Thestress suppressing features 134 are on either side of the NMOStransistor 102, positioned parallel to the direction of the NMOS gate108, and perpendicular to the direction of the strain.

Referring now to FIG. 3, therein is shown a top view of an IC 300according to an alternate embodiment of the present invention. An STI332 surrounds an NMOS transistor 302 and a PMOS transistor 304. The STI332 produces strain in the NMOS transistor 302 and the PMOS transistor304.

The NMOS transistor 302 is comprised of an NMOS gate 308, and an NMOSsource/drain 318 is on either side of the NMOS gate 308. In thisembodiment, stress suppressing features 334 surround the NMOS transistor302. Thus the stress suppressing features 334 lie perpendicular andparallel to the NMOS gate 308.

Electron mobility in the NMOS transistor 302 is degraded when stress isapplied in both perpendicular and parallel directions to the NMOS gate308. Thus, the stress suppressing features 334 reduce the stress in boththe perpendicular and parallel directions.

The PMOS transistor 304 is comprised of a PMOS gate 320, and a PMOSsource/drain 330 is on either side of the PMOS gate 320. In thisembodiment, the stress suppressing feature 334 lies perpendicular to thePMOS gate 320 and parallel to the direction of the strain.

Hole mobility is degraded, and thus performance is degraded, when stressis applied parallel to the PMOS gate 320. On the other hand, holemobility is improved, and thus performance is improved, when stress isapplied perpendicular to the PMOS gate 320. Thus, performance of thePMOS transistor 304 is increased when the stress suppressing feature 334lies perpendicular to the PMOS gate 320 and does not lie parallel to thePMOS gate 320.

Referring now to FIG. 4, therein is shown a flow chart of a system 400for an integrated circuit stress control system in accordance with thepresent invention. The system 400 includes providing a substrate in ablock 402; forming a gate on the substrate in a block 404; forming achannel in the substrate in a block 406; forming a source/drain aroundthe gate in a block 408; forming a shallow trench isolation in thesubstrate, the shallow trench isolation producing strain on the channelin a block 410; and forming a stress suppressing feature in thesubstrate in a block 412.

In greater detail, an integrated circuit stress control system,according to the present invention, is performed as follows:

-   -   (1) 1. As shown in FIG. 1, the substrate 106 is provided and the        NMOS channel 112 and the PMOS channel 124 are formed in the        substrate 106. The NMOS gate oxide 110 is formed over the NMOS        channel 112, and the PMOS gate oxide 122 is formed over the PMOS        channel 124. The NMOS gate 108 is formed on the NMOS gate oxide        110, and the PMOS gate 120 is formed on the PMOS gate oxide 122.        The NMOS liner 114 is formed around the NMOS gate 108, and the        PMOS liner 126 is formed around the PMOS gate 120. The NMOS        spacer 116 is formed on the NMOS liner 114, and the PMOS spacer        128 is formed on the PMOS liner 126. The NMOS source/drain 118        is formed around the NMOS gate 108, and the PMOS source/drain        130 is formed around the PMOS gate 120. The shallow trench        isolation 132, producing strain on the NMOS channel 112 and the        PMOS channel 124, is formed in the substrate 106. In addition, a        stress suppressing feature 134, relieving strain from the NMOS        channel 112, is formed in the substrate 106 and parallel to the        NMOS gate 108.    -   (2) 2. As shown in FIG. 3, elements are provided similar to FIG.        1 with differences to the stress suppressing feature 134 (FIG.        1). FIG. 3 has a stress suppressing feature 334 surrounding an        NMOS transistor 302, having been formed perpendicular and        parallel to the NMOS gate 308. In addition, the stress        suppressing feature 334 has been formed perpendicular to the        PMOS gate 320.

Thus, it has been discovered that the integrated circuit stress controlsystem of the present invention furnish important and heretofore unknownand unavailable solutions, capabilities, and functional advantages forsuppressing stress. The resulting process and configurations arestraightforward, economical, uncomplicated, highly versatile, andeffective, and can be implemented by adapting known components for readymanufacturing, application, and utilization.

While the invention has been described in conjunction with a specificbest mode, it is to be understood that many alternatives, modifications,and variations will be apparent to those skilled in the art in light ofthe aforegoing description. Accordingly, it is intended to embrace allsuch alternatives, modifications, and variations which fall within thescope of the included claims. All matters hithertofore set forth hereinor shown in the accompanying drawings are to be interpreted in anillustrative and non-limiting sense.

1. An integrated circuit stress control system comprising; providing asubstrate; forming a gate on the substrate; forming a channel in thesubstrate; forming a source/drain around the gate; forming a shallowtrench isolation in the substrate, the shallow trench isolationproducing strain on the channel; and forming a stress suppressingfeature in the substrate.
 2. The system of claim 1 wherein forming achannel in the substrate further comprises forming an n-type channel inthe substrate.
 3. The system of claim 1 wherein forming a channel in thesubstrate further comprises forming a p-type channel in the substrate.4. The system of claim 1 further comprising forming a plurality of thestress suppressing features that are parallel to the gate, perpendicularto the gate, or both parallel and perpendicular to the gate.
 5. Thesystem of claim 1 further comprising adjusting the strain to apredetermined level by adjusting the position of the stress suppressingfeature.
 6. An integrated circuit stress control system comprising;providing a substrate; forming a plurality of complementary metal oxidesemiconductors in the substrate; forming a shallow trench isolation inthe substrate, the shallow trench isolation producing strain in thecomplementary metal oxide semiconductors; and forming a plurality ofstress suppressing features in the substrate.
 7. The system of claim 6wherein forming a complementary metal oxide semiconductor furthercomprises forming a complementary metal oxide semiconductor with ann-type channel.
 8. The system of claim 6 wherein forming a complementarymetal oxide semiconductor further comprises forming a complementarymetal oxide semiconductor with a p-type channel.
 9. The system of claim6 wherein forming a plurality of stress suppressing features furthercomprises forming the stress suppressing features parallel to thedirection of the strain, perpendicular to the direction of the strain,or both parallel and perpendicular to the direction of the strain. 10.The system of claim 6 further comprising adjusting the strain to apredetermined level by adjusting the position of the stress suppressingfeature.
 11. An integrated circuit stress control system comprising; asubstrate; a gate on the substrate; a channel in the substrate; asource/drain around the gate; a shallow trench isolation in thesubstrate, the shallow trench isolation producing strain on the channel;and a stress suppressing feature in the substrate.
 12. The system ofclaim 11 wherein the channel in the substrate further comprises ann-type channel in the substrate.
 13. The system of claim 11 wherein thechannel in the substrate further comprises a p-type channel in thesubstrate.
 14. The system of claim 11 further comprising a plurality ofstress suppressing features in the substrate that are parallel to thegate, perpendicular to the gate, or both parallel and perpendicular tothe gate.
 15. The system of claim 11 wherein the stress suppressingfeature further comprises a stress suppressing feature configured andpositioned in the substrate to provide a predetermined level of strain.16. An integrated circuit stress control system comprising: a substrate;a plurality of complementary metal oxide semiconductors in thesubstrate; a shallow trench isolation in the substrate, the shallowtrench isolation producing strain in the complementary metal oxidesemiconductors; and a plurality of stress suppressing features in thesubstrate.
 17. The system of claim 16 wherein the complementary metaloxide semiconductor further comprises a complementary metal oxidesemiconductor with an n-type channel.
 18. The system of claim 16 whereinthe complementary metal oxide semiconductor further comprises acomplementary metal oxide semiconductor with a p-type channel.
 19. Thesystem of claim 16 wherein the stress suppressing features furthercomprise stress suppressing features formed parallel to the direction ofthe strain, perpendicular to the direction of the strain, or bothparallel and perpendicular to the direction of the strain.
 20. Thesystem of claim 16 wherein the stress suppressing features furthercomprise stress suppressing features configured and positioned in thesubstrate to provide a predetermined level of strain.